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82541ER Gigabit Ethernet Controller
Networking Silicon
Datasheet
Product Features
PCI Bus -- PCI revision 2.3, 32-bit, 33/66 MHz -- Algorithms that optimally use advanced PCI, MWI, MRM, and MRL commands -- 3.3 V (5 V tolerant PCI signaling) MAC Specific -- Low-latency transmit and receive queues -- IEEE 802.3x-compliant flow-control support with software-controllable thresholds -- Caches up to 64 packet descriptors in a single burst -- Programmable host memory receive buffers (256 B to 16 KB) and cache line size (16 B to 256 B) -- Wide, optimized internal data path architecture -- 64 KB configurable Transmit and Receive FIFO buffers PHY Specific -- Integrated for 10/100/1000 Mb/s operation -- IEEE 802.3ab Auto-Negotiation support -- IEEE 802.3ab PHY compliance and compatibility -- State-of-the-art DSP architecture implements digital adaptive equalization, echo cancellation, and cross-talk cancellation

-- Automatic polarity detection -- Automatic detection of cable lengths and MDI vs. MDI-X cable at all speeds Host Off-Loading -- Transmit and receive IP, TCP, and UDP checksum off-loading capabilities -- Transmit TCP segmentation -- Advanced packed filtering -- Jumbo frame support up to 16 KB -- Intelligent Interrupt generation (multiple packets per interrupt) Manageabiltiy -- Network Device Class Power Management Specification 1.1 -- Compliance with PCI Power Management 1.1 and ACPI 2.0 -- SNMP and RMON statistic counters -- D0 and D3 power states Additional Device -- Four programmable LED outputs -- On-chip power control circuitry -- BIOS LAN Disable pin -- JTAG (IEEE 1149.1) Test Access Port built in silicon Lead-freea 196-pin Ball Grid Array (BGA). Devices that are lead-free are marked with a circled "e1" and have the product code: LUxxxxxx.
a. This device is lead-free. That is, lead has not been intentionally added, but lead may still exist as an impurity at <1000 ppm. The Material Declaration Data Sheet, which includes lead impurity levels and the concentration of other Restriction on Hazardous Substances (RoHS)-banned materials, is available at: ftp://download.intel.com/design/packtech/material_content_IC_Package.pdf#pagemode=bookmarks In addition, this device has been tested and conforms to the same parametric specifications as previous versions of the device. For more information regarding lead-free products from Intel Corporation, contact your Intel Field Sales representative
Revision 4.1 September 2006
Revision History
Date Aug 2003 Mar 2004 Oct 2004 Revision 2.0 3.0 3.1 Non-classified release. Updated Section 4, "Voltage, Temperature, and Timing Specifications," for the C-0 stepping. * * Corrected EEMODE signal description. Updated signal names to match design guide and reference schematics. * Added lead free information. * Added information about migrating from a 2-layer 0.36 mm wide-trace substrate to a 2-layer 0.32 mm wide-trace substrate. Refer to the section on Package and Pinout Information. Nov 2004 3.2 * Added statement that no changes to existing soldering processes are needed for the 2-layer 0.32 mm wide-trace substrate change in the section describing "Package Information". * Corrected pinout discrepancies between sections "Signal Descriptions" and "Package and Pinout Information". * Added new maximum values for DC supply voltages on 1.2 V and 1.8 V pins. See Table 2, Recommended Operating Conditions and Table 6, DC Characteristics. * Updated Visual Pin Assignment diagram for pinouts F9, F10, E14, F14, and H14. * Removed all references to CLK_RUN# signal. Apr 2005 July 2005 Aug 2005 June 2006 June 2006 Aug 2006 Sept 2006 3.5 3.6 3.7 3.8 3.9 4.0 4.1 * Corrected the FLSH_SO/LAN_DISABLE signal definition. If Flash functionality is not used then an external pull-down resistor is required. * Added pin C8 description to Table 29 and Table 31. * Corrected 25 MHz Clock Input Requirements in Table 13. * Corrected the FLSH_SO/LAN_DISABLE signal definition. If Flash functionality is not used then an external pull-up resistor is required. * Updated Table 13 "25 MHz Clock Input Requirements". * Updated Table 40 descriptions for pins A10, B10, and C9. * Updated pinout descriptions from Tables 25 - 42 to match Figure 13. * Removed note "b" from Table 2 and note "a" from Tables 3 and 4. Moved the note following Table 5 before Table 3 "3.3V Supply Voltage Ramp". Notes
Jan 2005
3.3
Feb 2005
3.4
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The 82541ER Gigabit Ethernet Controller may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800548-4725 or by visiting Intel's website at http://www.intel.com. Intel(R) is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries. Copyright (c) Intel Corporation, 2006 *Third-party brands and names are the property of their respective owners.
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82541ER Gigabit Ethernet Controller
Contents
1.0 Introduction ...................................................................................................................... 1 1.1 1.2 1.3 1.4 2.0 3.0 Document Scope................................................................................................... 1 Reference Documents...........................................................................................2 Product Codes....................................................................................................... 2 Block Diagram ....................................................................................................... 3
Product Code.................................................................................................................... 5 Signal Descriptions.......................................................................................................... 7 3.1 3.2 Signal Type Definitions.......................................................................................... 7 PCI Bus Interface Signals (56) ..............................................................................7 3.2.1 PCI Address, Data and Control Signals (44) ............................................ 8 3.2.2 Arbitration Signals (2)............................................................................... 9 3.2.3 Interrupt Signal (1)....................................................................................9 3.2.4 System Signals (3) ................................................................................... 9 3.2.5 Error Reporting Signals (2).....................................................................10 3.2.6 Power Management Signals (2) .............................................................10 EEPROM and Serial FLASH Interface Signals (9)..............................................10 Miscellaneous Signals.........................................................................................11 3.4.1 LED Signals (4) ......................................................................................11 3.4.2 Other Signals (4) ....................................................................................11 PHY Signals ........................................................................................................11 3.5.1 Crystal Signals (2) ..................................................................................11 3.5.2 Analog Signals (10) ................................................................................12 Test Interface Signals (6) ....................................................................................12 Power Supply Connections .................................................................................13 3.7.1 Digital and Analog Supplies ...................................................................13 3.7.2 Grounds, Reserved Pins and No Connects ...........................................13 3.7.3 Voltage Regulation Control Signals (2) ..................................................13 Absolute Maximum Ratings.................................................................................15 Targeted Recommended Operating Conditions..................................................15 4.2.1 General Operating Conditions................................................................15 4.2.2 Voltage Ramp and Sequencing Recommendations...............................16 DC Specifications ................................................................................................18 AC Characteristics...............................................................................................21 Timing Specifications ..........................................................................................23 4.5.1 PCI Bus Interface ...................................................................................23 4.5.1.1 PCI Bus Interface Clock ............................................................23 4.5.1.2 PCI/PCI-X Bus Interface Timing ................................................24 4.5.2 Link Interface Timing ..............................................................................27 4.5.3 EEPROM Interface.................................................................................27 Package Information ...........................................................................................29 Thermal Specifications ........................................................................................31
3.3 3.4
3.5
3.6 3.7
4.0
Voltage, Temperature, and Timing Specifications ......................................................15 4.1 4.2
4.3 4.4 4.5
5.0
Package and Pinout Information ..................................................................................29 5.1 5.2
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82541ER Gigabit Ethernet Controller
5.3 5.4
Pinout Information ............................................................................................... 32 Visual Pin Assignments....................................................................................... 42
Figures
1 2 3 4 5 6 7 8 9 10 11 12 13 82541ER Block Diagram....................................................................................... 3 AC Test Loads for General Output Pins.............................................................. 23 PCI Clock Timing ................................................................................................ 23 PCI Bus Interface Output Timing Measurement ................................................. 24 PCI Bus Interface Input Timing Measurement Conditions .................................. 25 TVAL (max) Rising Edge Test Load.................................................................... 25 TVAL (max) Falling Edge Test Load ................................................................... 26 TVAL (min) Test Load ......................................................................................... 26 TVAL Test Load (PCI 5 V Signaling Environment) ............................................. 26 Link Interface Rise/Fall Timing............................................................................ 27 82541ER Mechanical Specifications................................................................... 29 196 PBGA Package Pad Detail........................................................................... 30 Visual Pin Assignments....................................................................................... 42
Tables
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Absolute Maximum Ratings ................................................................................ 15 Recommended Operating Conditions ................................................................ 15 3.3V Supply Voltage Ramp ................................................................................. 16 1.8V Supply Voltage Ramp ................................................................................. 16 1.2V Supply Voltage Ramp ................................................................................. 17 DC Characteristics .............................................................................................. 18 Power Specifications - D0a ................................................................................. 18 Power Specifications - D3cold ............................................................................ 18 Power Specifications D(r) Uninitialized) .............................................................. 19 Power Specifications - Complete Subsystem ..................................................... 19 I/O Characteristics............................................................................................... 20 AC Characteristics: 3.3 V Interfacing .................................................................. 21 25 MHz Clock Input Requirements ..................................................................... 21 Reference Crystal Specification Requirements................................................... 22 Link Interface Clock Requirements ..................................................................... 22 EEPROM Interface Clock Requirements ............................................................ 22 AC Test Loads for General Output Pins.............................................................. 22 PCI Bus Interface Clock Parameters .................................................................. 23 PCI Bus Interface Timing Parameters................................................................. 24 PCI Bus Interface Timing Measurement Conditions ........................................... 25 Rise and Fall Times ............................................................................................ 27 Link Interface Clock Requirements ..................................................................... 27 Link Interface Clock Requirements ..................................................................... 27 Thermal Characteristics ...................................................................................... 31 PCI Address, Data and Control Signals .............................................................. 32 PCI Arbitration Signals ........................................................................................ 32 Interrupt Signals .................................................................................................. 32 System Signals ................................................................................................... 32 Error Reporting Signals....................................................................................... 33 Power Management Signals ............................................................................... 33 Serial EEPROM Interface Signals....................................................................... 33
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32 33 34 35 36 37 38 39 40 41 42
Serial FLASH Interface Signals...........................................................................33 LED Signals.........................................................................................................33 Other Signals.......................................................................................................33 IEEE Test Signals ...............................................................................................34 PHY Signals ........................................................................................................34 Test Interface Signals..........................................................................................34 Digital Power Signals ..........................................................................................34 Analog Power Signals .........................................................................................35 Grounds and No Connect Signals.......................................................................35 Voltage Regulation Control Signals.....................................................................35 Signal Names in Pin Order..................................................................................36
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82541ER Gigabit Ethernet Controller
1.0
Introduction
The Intel(R) 82541ER Gigabit Ethernet is a single, compact component with an integrated Gigabit Ethernet Media Access Control (MAC) and physical layer (PHY) functions. For embedded communication and network devices such as web kiosks, and Point-of-Sale terminal designs with critical space constraints, the Intel 82541ER allows for a Gigabit Ethernet implementation in a very small area that is footprint compatible with current generation 10/100 Mbps Fast Ethernet designs. The Intel(R) 82541ER integrates fourth generation gigabit MAC design with fully integrated, physical layer circuitry to provide a standard IEEE 802.3 Ethernet interface for 1000BASE-T, 100BASE_TX, and 10BASE-T applications (802.3, 802.3u, and 802.3ab). The controller is capable of transmitting and receiving data at rates of 1000 Mbps, 100 Mbps, or 10 Mbps. In addition to managing MAC and PHY layer functions, the controller provides a 32-bit wide direct Peripheral Component Interconnect (PCI) 2.3 compliant interface capable of operating at 33 or 66 MHz. The 82541ER Architecture is designed for high performance and low memory latency. Wide internal data paths eliminate performance bottlenecks by efficiently handling large address and data words. The 82541ER controller includes advanced interrupt handling features to limit PCI bus traffic and a PCI interface that maximizes efficient bus usage. The 82541ER uses efficient ring buffer descriptor data structures, with up to 64 packet descriptors cached on chip. A large 64 KByte on-chip packet buffer maintains superior performance as available PCI bandwidth changes. In addition, using hardware acceleration, the controller offloads tasks from the host controller, such as TCP/UDP/IP checksum calculations and TCP segmentation. The 82541ER is packaged in a 15 mm X 15 mm 196-ball grid array and is pin compatible with the 82559ER/82551ER 10/100 Mbps Fast Ethernet Multifunction PCI/CardBus Controller, 82562EZ/ 82562EX Platform LAN Connect devices, the 82540EM Gigabit Ethernet Controller and the 82540EP Gigabit Ethernet Controller.
1.1
Document Scope
This document contains datasheet specifications for the 82541ER Gigabit Ethernet Controller, including signal descriptions, DC and AC parameters, packaging data, and pinout information.
Datasheet
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82541ER Gigabit Ethernet Controller
1.2
Reference Documents
This document assumes that the designer is acquainted with high-speed design and board layout techniques. The following documents provide additional information:
* 825462EZ(EX)/82551ER(IT) & 82541ER Combined Footprint LOM Design Guide. Intel
Corporation.
* 82547GI(EI)/82541(PI/GIEI) & 82541ER EEPROM Map and Programming Information
Guide. Intel Corporation.
* PCI Local Bus Specification, Revision 2.3. PCI Special Interest Group. * PCI Bus Power Management Interface Specification, Revision 1.1. PCI Special Interest
Group.
* IEEE Standard 802.3, 2003 Edition. Incorporates various IEEE standards previously published
separately. Institute of Electrical and Electronics Engineers (IEEE).
* Intel Ethernet Controllers Timing Device Selection Guide. Intel Corporation. * PCI Mobile Design Guide, Revision 1.1. PCI Special Interest Group.
Software driver developers should contact their local Intel representatives for programming information.
1.3
Product Codes
The product ordering codes are:
* GD82541ER * LU82541ER
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82541ER Gigabit Ethernet Controller
1.4
Block Diagram
PCI Core
EEPROM
Flash
Slave Access Logic
DMA Function Descriptor Management 64KB Packet RAM
Control Status Logic
TX/RX MAC CSMA/CD VLA N
RX FIlters (Perfect & VLAN)
Statistics
8 bits 8 bits
Management Interface Side-stream Scrambler/ Descrambler
Trellis Viterbi Encoder/Decoder
4 bits 4 bits
PHY Control
ECHO, NEXT, FEXT Cancellers AGC, A/D Timing Recovery
4DPAM5 Encoder
Pulse Shaper, DAC, Filter
Hybrid
Line Driver
Media Dependent Interface
Figure 1. 82541ER Block Diagram
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2.0
Product Code
The product code for the 82541ER Gigabit Ethernet Controller is: GD82541ER.
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3.0
3.1
Signal Descriptions
Signal Type Definitions
The signals of the 82541ER controller are electrically defined as follows:
Name
I O TS
Definition Input. Standard input only digital signal. Output. Standard output only digital signal. Tri-state. Bi-directional tri-state digital input/output signal. Sustained Tri-state. An active low tri-state signal owned and driven by only one agent at a time. The agent that drives an STS pin low must drive it high for at least one clock before letting it float. A new agent cannot start driving an STS signal any sooner than one clock after the previous owner tri-states it. A pullup is required to sustain the inactive state until another agent drives it, and must be provided by the central resource. Open Drain. Wired-OR with other agents.
The signaling agent asserts the OD signal, but the signal is returned to the inactive state by a weak pull-up resistor. The pull-up resistor may require two or three clock periods to fully restore the signal to the de-asserted state.
STS
OD
A P
Analog. PHY analog data signal. Power. Power connection, voltage reference, or other reference connection.
3.2
PCI Bus Interface Signals (56)
When the Reset signal (RST#) is asserted, the 82541ER will not drive any PCI output or bidirectional pins.
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82541ER Gigabit Ethernet Controller
3.2.1
PCI Address, Data and Control Signals (44)
Symbol Type Name and Function Address and Data. Address and data signals are multiplexed on the same PCI pins. A bus transaction includes an address phase followed by one or more data phases.
The address phase is the clock cycle when the Frame signal (FRAME#) is asserted low. During the address phase AD[31:0] contain a physical address (32 bits). For I/O, this is a byte address, and for configuration and memory, a DWORD address. The 82541ER device uses little endian byte ordering. During data phases, AD[7:0] contain the least significant byte (LSB) and AD[31:24] contain the most significant byte (MSB).
AD[31:0]
TS
C/BE#[3:0]
TS
Bus Command and Byte Enables. Bus command and byte enable signals are multiplexed on the same PCI pins. During the address phase of a transaction, C/ BE#[3:0] define the bus command. In the data phase, C/BE#[3:0] are used as byte enables. The byte enables are valid for the entire data phase and determine which byte lanes contain meaningful data.
C/BE#[0] applies to byte 0 (LSB) and C/BE#[3] applies to byte 3 (MSB).
PAR
TS
Parity. The Parity signal is issued to implement even parity across AD[31:0] and C/ BE#[3:0]. PAR is stable and valid one clock after the address phase. During data phases, PAR is stable and valid one clock after either IRDY# is asserted on a write transaction or TRDY# is asserted after a read transaction. Once PAR is valid, it remains valid until one clock after the completion of the current data phase.
When the 82541ER controller is a bus master, it drives PAR for address and write data phases, and as a slave device, drives PAR for read data phases.
FRAME#
STS
Cycle Frame. The Frame signal is driven by the 82541ER device to indicate the beginning and length of a bus transaction.
While FRAME# is asserted, data transfers continue. FRAME# is de-asserted when the transaction is in the final data phase.
IRDY#
STS
Initiator Ready. Initiator Ready indicates the ability of the 82541ER controller (as a bus master device) to complete the current data phase of the transaction. IRDY# is used in conjunction with the Target Ready signal (TRDY#). The data phase is completed on any clock when both IRDY# and TRDY# are asserted.
During the write cycle, IRDY# indicates that valid data is present on AD[31:0]. For a read cycle, it indicates the master is ready to accept data. Wait cycles are inserted until both IRDY# and TRDY# are asserted together. The 82541ER controller drives IRDY# when acting as a master and samples it when acting as a slave.
TRDY#
STS
Target Ready. The Target Ready signal indicates the ability of the 82541ER controller (as a selected device) to complete the current data phase of the transaction. TRDY# is used in conjunction with the Initiator Ready signal (IRDY#). A data phase is completed on any clock when both TRDY# and IRDY# are sampled asserted.
During a read cycle, TRDY# indicates that valid data is present on AD[31:0]. For a write cycle, it indicates the target is ready to accept data. Wait cycles are inserted until both IRDY# and TRDY# are asserted together. The 82541ER device drives TRDY# when acting as a slave and samples it when acting as a master.
STOP#
STS
Stop. The Stop signal indicates the current target is requesting the master to stop the current transaction. As a slave, the 82541ER controller drives STOP# to request the bus master to stop the transaction. As a master, the 82541ER controller receives STOP# from the slave to stop the current transaction.
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82541ER Gigabit Ethernet Controller
Symbol
IDSEL#
Type
I
Name and Function Initialization Device Select. The Initialization Device Select signal is used by the 82541ER as a chip select signal during configuration read and write transactions. Device Select. When the Device Select signal is actively driven by the 82541ER, it signals notifies the bus master that it has decoded its address as the target of the current access. As an input, DEVSEL# indicates whether any device on the bus has been selected. VIO. The VIO signal is a voltage reference for the PCI interface (3.3 V or 5 V PCI signaling environment). It is used as the clamping voltage. Note: VIO should be connected to 3.3V Aux or 5V Aux in order to be compatible with the pull-up clamps specification.
DEVSEL#
STS
VIO
P
3.2.2
Arbitration Signals (2)
Symbol
REQ# GNT#
Type
TS I
Name and Function Request Bus. The Request Bus signal is used to request control of the bus from the arbiter. This signal is point-to-point. Grant Bus. The Grant Bus signal notifies the 82541ER that bus access has been granted. This is a point-to-point signal.
3.2.3
Interrupt Signal (1)
Symbol
INTA#
Type
TS
Name and Function Interrupt A. Interrupt A is used to request an interrupt of the 82541ER. It is an active low, level-triggered interrupt signal.
3.2.4
System Signals (3)
Symbol Type Name and Function PCI Clock. The PCI Clock signal provides timing for all transactions on the PCI bus and is an input to the 82541ER device. All other PCI signals, except the Interrupt A (INTA#) and PCI Reset signal (RST#), are sampled on the rising edge of CLK. All other timing parameters are defined with respect to this edge. 66 MHz Enable. M66EN indicates whether the system bus is enabled for 66MHz PCI Reset. When the PCI Reset signal is asserted, all PCI output signals are floated and all input signals are ignored.
Most of the internal state of the 82541ER is reset on the de-assertion (rising edge) of RST#.
CLK
I
M66EN
I
RST#
I
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82541ER Gigabit Ethernet Controller
3.2.5
Error Reporting Signals (2)
Symbol
SERR#
Type
OD
Name and Function System Error. The System Error signal is used by the 82541ER controller to report address parity errors. SERR# is open drain and is actively driven for a single PCI clock when reporting the error. Parity Error. The Parity Error signal is used by the 82541ER controller to report data parity errors during all PCI transactions except by a Special Cycle. PERR# is sustained tri-state and must be driven active by the 82541ER controller two data clocks after a data parity error is detected. The minimum duration of PERR# is one clock for each data phase a data parity error is present.
PERR#
STS
3.2.6
Power Management Signals (2)
Symbol
LAN_PWR GOOD AUX_PWR
Type
I
Name and Function Power Good (Power-on Reset). The Power Good signal is used to indicate that stable power is available for the 82541ER. When the signal is low, the 82541ER holds itself in reset state and floats all PCI signals. Auxiliary Power. If the Auxiliary Power signal is high, then auxiliary power is available and the 82541ER device should support the D3cold power state.
I
3.3
EEPROM and Serial FLASH Interface Signals (9)
Symbol Type Name and Function EEPROM Mode. The EEPROM Mode pin is used to select the interface and source of the EEPROM used to initialize the device. For a MIcrowire* EEPROM on the standard EEPROM pins, tie this pin to ground with a 100 pull-down resistor.
For a Serial Peripheral Interface (SPI*) EEPROM, leave this pin disconnected. EEDI O
EEMODE
I
EEPROM Data Input. The EEPROM Data Input pin is used for output to the memory device. EEPROM Data Output. The EEPROM Data Output pin is used for input from the memory device. The EEDO includes an internal pull-up resistor.
Note: Voltage for EEDO must be less than 0.7 V.
EEDO
I
EECS
O
EEPROM Chip Select. The EEPROM Chip Select signal is used to enable the device. EEPROM Serial Clock. The EEPROM Shift Clock provides the clock rate for the EEPROM interface, which is approximately 1 MHz for Microwire* and 2 MHZ for SPI. Flash Chip Enable Output. Used to enable FLASH device. Flash Serial Clock Output. The clock rate of the serial FLASH interface is approximately 1 MHz. Flash Serial Data Input. This pin is an output to the memory device. Flash Serial Data Output / LAN Disable. This pin is an input from the Flash memory. Alternatively, the pin can be used to disable the LAN port from a system General Purpose Input Output (GPIO) port. It has an internal pullup device. If the 82541ER is not using Flash functionality, the pin should be connected to an external pull-up resistor.
If this pin is used as LAN_DISABLE#, the device goes to low power state and the LAN port is disabled when this pin is sampled low on rising edge of PCI reset.
EESK FLSH_CE# FLSH_SCK FLSH_SI
O O O O
FLSH_SO/ LAN_DISABLE#
I
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82541ER Gigabit Ethernet Controller
3.4
3.4.1
Miscellaneous Signals
LED Signals (4)
Symbol
LINK_LED# ACTIVITY# LINK100# LINK1000#
Type
O O O O
Name and Function LED0 / LINK Up. Programmable LED indication. Defaults to indicate link connectivity. LED1 / Activity. Programmable LED indication. Defaults to flash to indicate transmit or receive activity. LED2 / LINK 100. Programmable LED indication. Defaults to indicate link at 100 Mbps. LED3 / LINK 1000. Programmable LED indication. Defaults to indicate link at 1000 Mbps.
3.4.2
Other Signals (4)
Symbol
Type
Name and Function Software Defined Pin. The Software Defined Pins are reserved and programmable with respect to input and output capability. These default to input signals upon power-up but may be configured differently by the EEPROM. The upper four bits may be mapped to the General Purpose Interrupt bits if they are configured as input signals.
SDP[3:0]
TS
3.5
3.5.1
PHY Signals
Crystal Signals (2)
Symbol
XTAL1 XTAL2
Type
I O
Name and Function Crystal One. The Crystal One pin is a 25 MHz +/- 50 ppm input signal. It should be connected to a crystal, and the other end of the crystal should connect to XTAL2. Crystal Two. Crystal Two is the output of an internal oscillator circuit used to drive a crystal into oscillation.
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3.5.2
Analog Signals (10)
Symbol
Type
Name and Function Media Dependent Interface [0]. 1000BASE-T: In MDI configuration, MDI[0]+/- corresponds to BI_DA+/-, and in MDI-X configuration, MDI[0]+/- corresponds to BI_DB+/-.
MDI[0]+/-
A
100BASE_TX: In MDI configuration, MDI[0]+/- is used for the transmit pair, and in MDI-X configuration, MDI[0]+/- is used for the receive pair. 10BASE-T: In MDI configuration, MDI[0]+/- is used for the transmit pair, and in MDI-X configuration, MDI[0]+/- is used for the receive pair. Media Dependent Interface [1]. 1000BASE-T: In MDI configuration, MDI[1]+/- corresponds to BI_DB+/-, and in MDI-X configuration, MDI[1]+/- corresponds to BI_DA+/-.
MDI[1]+/-
A
100BASE_TX: In MDI configuration, MDI[1]+/- is used for the receive pair, and in MDI-X configuration, MDI[1]+/- is used for the transit pair. 10BASE-T: In MDI configuration, MDI[1]+/- is used for the receive pair, and in MDI-X configuration, MDI[1]+/- is used for the transit pair. Media Dependent Interface [2]. 1000BASE-T: In MDI configuration, MDI[2]+/- corresponds to BI_DC+/-, and in MDIX configuration, MDI[2]+/- corresponds to BI_DD+/-. 100BASE_TX: Unused. 10BASE-T: Unused. Media Dependent Interface [3]. 1000BASE-T: In MDI configuration, MDI[3]+/- corresponds to BI_DC+/-, and in MDIX configuration, MDI[3]+/- corresponds to BI_DD+/-. 100BASE_TX: Unused. 10BASE-T: Unused. IEEE test pin output minus. Used to gain access to the internal PHY clock for 1000BASE-T IEEE physical layer conformance testing. Analog test pin output plus. Used to gain access to the internal PHY clock for 1000BASE-T IEEE physical layer conformance testing.
MDI[2]+/-
A
MDI[3]+/-
A
IEEE_TESTIEEE_TEST+
A A
3.6
Test Interface Signals (6)
Symbol
TEST JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST#
Type
I I I O I I
Name and Function Test Enable. Enables test mode.
Normal mode: connect to VSS.
JTAG Test Access Port Clock. JTAG Test Access Port Data In. JTAG Test Access Port Data Out. JTAG Test Access Port Mode Select. JTAG Test Access Port Reset. This is an active low reset signal for JTAG. To disable the JTAG interface, this signal should be terminated using a 100 pull-down resistor to ground. It must not be left unconnected.
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3.7
3.7.1
Power Supply Connections
Digital and Analog Supplies
Symbol
3.3V Analog_1.8V CLKR_1.8V XTAL_1.8V 1.2V Analog_1.2V PLL_1.2V
Type
P P P P P P P
Name and Function 3.3 V I/O Power Supply. 1.8V Analog Power Supply. 1.8V analog power supply for the clock recovery. Input power for the XTAL regulator. 1.2V Power supply. This is for analog and digital circuits. 1.2V Analog Power Supply. Input power for the ICS regulator.
3.7.2
Grounds, Reserved Pins and No Connects
Symbol
VSS AVSS RSVD_VSS
Type
P P P
Name and Function Ground. Shared analog Ground. Reserved Ground. This pin is reserved by Intel and may have factory test functions. For normal operation, connect to ground. Reserved No connect. This pin is reserved by Intel and may have factory test functions. For normal operation, do not connect any circuit to these pins. Do not connect pull-up or pull-down resistors. No Connect. This pin is not connected internally. Reserved VCC. This pin is reserved by Intel and may have factory test functions. For normal operation, connect to VCC through a 1K pull-up resistor
RSVD_NC NC RSVD_VCC
P P P
3.7.3
Voltage Regulation Control Signals (2)
Symbol Type Name and Function 1.2V Control. LDO voltage regulator output to drive external PNP pass transistor. If 1.2V is already present in the system, leave output unconnected. To achieve optimal D3 power consumption, leave the output unconnected and use a high-efficiency external switching regulator. 1.8V Control. LDO voltage regulator output to drive external PNP pass transistor. If 1.8V is already present in the system, leave output unconnected. To achieve optimal D3 power consumption, leave the output unconnected and use a high-efficiency external switching regulator.
CTRL12
A
CTRL18
A
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82541ER Gigabit Ethernet Controller
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82541ER Gigabit Ethernet Controller
4.0
4.1
Table 1.
Voltage, Temperature, and Timing Specifications
Absolute Maximum Ratings
Absolute Maximum Ratingsa
Symbol VDD (3.3) VDD (1.8) VDD (1.2) VDD VI / VO IO TSTG Parameter DC supply voltage on 3.3 V pins with respect to VSS DC supply voltage on 1.8 V pins with respect to VSS DC supply voltage on 1.2V pins with respect to VSS DC supply voltage LVTTL input voltage Output current Storage temperature range ESD per MIL_STD-883 Test Method 3015, Specification 2001V Latchup Over/Undershoot: 150 mA, 125 C -40 Min VSS - 0.5 VSS - 0.5 VSS - 0.5 VSS - 0.5 VSS - 0.5 Max 4.6 2.5 or VDD (1.8) + 0.5b 1.7 or VDD (1.2) + 0.5c 4.6 4.6d 40 125 VDD overstress: VDD (3.3) * 7.2 Unit V V V V V mA C
V
a. Maximum ratings are referenced to ground (VSS). Permanent device damage is likely to occur if the ratings in this table are exceeded. These values should not be used as the limits for normal device operations. b. The maximum value is the lesser value of 2.5V or VDD (2.5) + 0.5 V. This specification applies to biasing the device to a steady state for an indefinite duration. c. The maximum value is the lesser value of 1.7 V or VDD (2.5) + 0.5 V. d. The maximum value must also be less than VIO.
4.2
4.2.1
Table 2.
Targeted Recommended Operating Conditions
General Operating Conditions
Recommended Operating Conditions (Sheet 1 of 2)a
Symbol VDD (3.3) VDD (1.8) VDD (1.2) VIO tR / tF Parameter DC supply voltage on 3.3 V pins DC supply voltage on 1.8 V pins DC supply voltage on 1.2 V pins PCI bus reference voltage Input rise/fall time (normal input) Min 3.0 1.71
b
Max 3.6 1.89
c
Unit V V V V ns
1.14d 3.0 0
1.26e 5.25 200
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15
82541ER Gigabit Ethernet Controller
Table 2.
Recommended Operating Conditions (Sheet 2 of 2)a
Symbol tr/tf TA TJ Parameter input rise/fall time (Schmitt input) Operating temperature range (ambient) Junction temperature Min 0 0 Max 10 70 125 Unit ms C C
a. Sustained operation of the device at conditions exceeding these values, even if they are within the absolute maximum rating limits, might result in permanent damage. b. The value listed in this table is for external voltage regulation. If the internal voltage regulator is used, the minimum value is 1.67 V. c. The value listed in this table is for external voltage regulation. If the internal voltage regulator is used, the maximum value is 1.926 V. d. The value listed in this table is for external voltage regulation. If the internal voltage regulator is used, the minimum value is 1.12 V. e. The value listed in this table is for external voltage regulation. If the internal voltage regulator is used, the maximum value is 1.284 V.
4.2.2
Note:
Voltage Ramp and Sequencing Recommendations
In any case or time period (greater than 1 ns), the supply voltage should comply with 3.3V > 1.8V > 1.2V. This is important to avoid stress in the ESD protection circuits. After 3.3V reaches 10% of its final value, all voltage rails (1.8V and 1.2V) have 150 ms to reach their final operating values. 3.3V Supply Voltage Ramp
Parameter Rise Time Monotonicity Slope Operational Range Ripple Overshoot Description Time from 10% to 90% mark Voltage dip allowed in ramp Ramp rate at any time between 10% to 90% Voltage range for normal operating conditions Maximum voltage ripple at a bandwidth equal to 50 MHz Maximum voltage allowed 3 Min 0.1 Max 100 0 28800 3.6 70 4 Unit ms mV V/s V mV V
Table 3.
Table 4.
1.8V Supply Voltage Ramp
Symbol Rise Time Monotonicity Slope Operational Range Operational Range Operational Range Operational Range Parameter Time from 10% to 90% mark Voltage dip allowed in ramp Ramp rate at any time between 10% to 90% Voltage range for normal operating conditions (PNP's)a Voltage range for normal operating conditions (PNP's) Voltage range for normal operating conditions (external regulator) Voltage range for normal operating conditions (external regulator) 1.674 -7 1.71 -5 Min 0.1 Max 100 0 57600 1.89 5 1.89 5 Unit ms mV V/s V % V %
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82541ER Gigabit Ethernet Controller
Table 4.
1.8V Supply Voltage Ramp
Ripple Overshoot Output Capacitance Input Capacitance Capacitance ESR Ictrl_18 Maximum voltage ripple at a bandwidth equal to 50 MHz Maximum voltage allowed Capacitance range when using PNP circuit Capacitance range when using PNP circuit Equivalent series resistance of output capacitanceb Maximum output current rating to CTRL18 4.7 4.7 5 20 2.2 20 20 100 20 mV V F F m mA
a. Operating with an internal regulator (PNP) supports a wider tolerance output voltage due to process tracking. b. Tantalum capacitors must not be used.
Table 5.
1.2V Supply Voltage Ramp
Symbol Rise Time Monotonicity Slope Operational Range Operational Range Operational Range Operational Range Ripple Overshoot Output Capacitance Input Capacitance Capacitance ESR Ictrl_12 Parameter Time from 10% to 90% mark Voltage dip allowed in ramp Ramp rate at any time between 10% to 90% Voltage range for normal operating conditions (PNP's)a Voltage range for normal operating conditions (PNP's) Voltage range for normal operating conditions (external regulator) Voltage range for normal operating conditions (external regulator) Maximum voltage ripple at a bandwidth equal to 50 MHz Maximum voltage allowed Capacitance range when using PNP circuit Capacitance range when using PNP circuit Equivalent series resistance of output capacitanceb Maximum output current rating to CTRL_12 4.7 4.7 5 1.116 -7 1.14 -5 Min 0.025 0 38400 1.26 5 1.26 5 20 1.45 20 20 100 20 Max Unit ms mV V/s V % V % mV V F F m mA
a. Operating with an internal regulator (PNP) supports a wider tolerance output voltage due to process tracking. b. Tantalum capacitors must not be used.
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82541ER Gigabit Ethernet Controller
4.3
Table 6.
DC Specifications
DC Characteristics
Symbol
VDD (3.3) VDD (1.8) VDD (1.2)
Parameter
DC supply voltage on 3.3 V pins DC supply voltage on 1.8 V pins DC supply voltage on 1.2 V pins
Condition
Min
3.00 1.71a 1.14c
Typ
3.3 1.8 1.2
Max
3.60 1.89b 1.26d
Units
V V V
a. The value listed in this table is for external voltage regulation. If the internal voltage regulator is used, the minimum value is 1.67 V. b. The value listed in this table is for external voltage regulation. If the internal voltage regulator is used, the maximum value is 1.926 V. c. The value listed in this table is for external voltage regulation. If the internal voltage regulator is used, the minimum value is 1.12 V. d. The value listed in this table is for external voltage regulation. If the internal voltage regulator is used, the maximum value is 1.284 V.
Table 7.
Power Specifications - D0a
D0a unplugged no link Typ Icc (mA)a 3.3V 1.8V 1.2V Total Device Power
3 14 30
@10 Mbps Typ Icc (mA)a
5 85 85
@100 Mbps Typ Icc (mA)a
13 110 90
@ 1000 Mbps Typ Icc (mA)a
30 315 380
Max Icc (mA)b
5 15 35
Max Icc (mA)b
10 85 90
Max Icc (mA)b
15 115 100
Max Icc (mA)b
40 320 400
75 mW
270 mW
355 mW
1.1 W
1.2 W
a. Typical conditions: operating temperature (TA) = 25 C, nominal voltages, moderate network traffic at full duplex, and PCI 33 MHz system interface. b. Maximum conditions: minimum operating temperature (TA) values, maximum voltage values, continuous network traffic at full duplex, and PCI 33 MHz system interface.
Table 8.
Power Specifications - D3cold
D3cold - wake-up enableda unplugged link Typ Icc (mA)b 3.3V
2
@10 Mbps Typ Icc (mA)a
2
@100 Mbps Typ Icc (mA)a
2
D3cold-wake disabled Typ Icc (mA)a
4
Max Icc (mA)c
3
Max Icc (mA)b
3
Max Icc (mA)b
3
Max Icc (mA)b
5
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82541ER Gigabit Ethernet Controller
Table 8.
Power Specifications - D3cold
D3cold - wake-up enableda unplugged link Typ Icc (mA)b 1.8V 1.2V Total Device Power
14 21
@10 Mbps Typ Icc (mA)a
20 30
@100 Mbps Typ Icc (mA)a
110 80
D3cold-wake disabled Typ Icc (mA)a
1 7
Max Icc (mA)c
15 25
Max Icc (mA)b
25 35
Max Icc (mA)b
115 85
Max Icc (mA)b
2 10
60 mW
80 mW
305 mW
25 mW
a. The power consumption for 1000 Mbps is not shown since the controller moves to the 10/100 Mbps mode before going into the D3 state to conserve power. b. Typical conditions: operating temperature (TA) = 25 C, nominal voltages, moderate network traffic at full duplex, and PCI 33 MHz system interface. c. Maximum conditions: minimum operating temperature (TA) values, maximum voltage values, continuous network traffic at full duplex, and PCI 33 MHz system interface.
Table 9.
Power Specifications D(r) Uninitialized)
D(r) Uninitialized (FLSH_SO/LAN_DISABLE # = 0) Typ Icc (mA) 3.3V 1.8V 1.2V Total Device Power
5 1 12
Max Icc (mA)
10 2 15
35 mW
Table 10. Power Specifications - Complete Subsystem
Complete Subsystem (Reference Design) Including Magnetics, LED, Regulator Circuits D3cold - wake disabled Max Icc (mA)b
5
D3cold wakeenabled @ 10 Mbps Typ Icc (mA)a
7
D0 @10 Mbps active Max Icc (mA)b
D0 @100 Mbps active Max Icc (mA)b
15
D0 @ 1000 Mbps active Typ Icc (mA)a
33
Typ Icc (mA)a 3.3 V
4
Max Icc (mA)b
10
Typ Icc (mA)a
Typ Icc (mA)a
12
Max Icc (mA)b
45
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82541ER Gigabit Ethernet Controller
Table 10. Power Specifications - Complete Subsystem
Complete Subsystem (Reference Design) Including Magnetics, LED, Regulator Circuits D3cold - wake disabled Max Icc (mA)b
7 7
D3cold wakeenabled @ 10 Mbps Typ Icc (mA)a
2 10
D0 @10 Mbps active Max Icc (mA)b
D0 @100 Mbps active Max Icc (mA)b
135 80
D0 @ 1000 Mbps active Typ Icc (mA)a
140 85
Typ Icc (mA)a 1.8 V 1.2 V Subsystem 3.3V Current
1
Max Icc (mA)b
30 30
Typ Icc (mA)a
Typ Icc (mA)a
35 35
Max Icc (mA)b
410 380
10
40
120
710
a. Typical conditions: operating temperature (TA) = 25 C, nominal voltages, moderate network traffic at full duplex, and PCI 33 MHz system interface. b. Maximum conditions: minimum operating temperature (TA) values, maximum voltage values, continuous network traffic at full duplex, and PCI 33 MHz system interface.
Table 11. I/O Characteristics (Sheet 1 of 2)
Symbol
VIH VIL
Parameter
Input high voltage Input low voltage Input current Input with pulldown resistor (50 K) Inputs with pull-up resistor (50 K)
Condition
3.3 V PCI 3.3 V PCIa 0 < VIN < VDD(3.3) VIN = VDD(3.3)
Min
0.5 * VDD(3.3) VSS -10 28
Typ
Max
VDD(3.3) or VIO 0.3 * VDD(3.3) 10 191
Units
V V
IIN
A
VIN = VSS 3.3 V PCI
-28
-191 2.09 100 * VOUT mA
IOL
Output low current
0 VOUT 3.6V 0 VOUT 1.3V 1.3V VOUT 3.6V 0 (VDD-VOUT) 3.6V 48 * VOUT 5.7 * VOUT+ 55
-74 * (VDD VOUT) -32 * (VDD VOUT) -11 * (VDD VOUT)-25.2 -1.8 * (VDD VOUT)-42.7 V
IOH
Output high current:
0 (VDD-VOUT) 1.2V 1.2V (VDD-VOUT) 1.9V 1.9V (VDD-VOUT) 3.6V
mA
VOH
Output high voltage: 3.3 V PCI IOH = -500 mA 0.9 * VDD(3.3)
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82541ER Gigabit Ethernet Controller
Table 11. I/O Characteristics (Sheet 2 of 2) (Continued)
Symbol Parameter
Output low voltage: 3.3 V PCI IOZ IOS CIN Off-state output leakage current Output short circuit current Input capacitanceb Input and bidirectional buffers 8 IOL = 1500 mA VO = VDD or VSS -10 0.1 * VDD(3.3) 10 -250 A mA pF
Condition
Min
Typ
Max
Units
VOL
V
a. The maximum VIL is 0.6 V for the following Pins: A13, C5, C8, J4, L7, L12, L13, M8, M12, M13, N10, N11, N13, N14, P9, and P13. b. VDD (3.3) = 0 V; TA = 25 C; f = 1 Mhz
4.4
AC Characteristics
Table 12. AC Characteristics: 3.3 V Interfacing
Symbol
PCICLK
Parameter
Clock frequency in PCI mode
Min
Typ
Max
66
Unit
MHz
Table 13. 25 MHz Clock Input Requirements
Specifications Symbol
f0 df0 Dc tr tf Jptp Cin T Aptp Vcm Frequency Frequency variation Duty cycle Rise time Fall time Clock jitter (peak-to-peak) Input capacitance Operating temperature Input clock amplitude (peak-to-peak) Clock common mode 1.0 1.2 0.6
a
Parameter Min Typ
25 -50 40 +30 60 5 5 250 20 70 1.3
Units Max
MHz ppm % ns ns ps pF C V V
a. Clock jitter is defined according to the recommendations of part 40.6.1.2.5 IEEE 1000BASE-T Standard (at least 105 clock edges, filtered by HPF with cut off frequency 5000 Hz).
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82541ER Gigabit Ethernet Controller
Table 14. Reference Crystal Specification Requirements
Specification
Vibrational Mode Nominal Frequency Frequency Tolerance Temperature Stability Calibration Mode Load Capacitance Shunt Capacitance Series Resistance, Rs Drive Level Aging Insulation Resistance Fundamental 25.000 MHz at 25 C 30 ppm 30 ppm at 0 C to 70 C Parallel 20 pF to 24 pF 6 pF maximum 50 W maximum 0.5 mW maximum 5.0 ppm per year maximum 500 M at DC 100 V
Value
Table 15. Link Interface Clock Requirements
Symbol
fGTX
a
Parameter
GTX_CLK frequency
Min
Typ
125
Max
Unit
MHz
a. GTX_CLK is used externally for test purposes only.
Table 16. EEPROM Interface Clock Requirements
Symbol
fSK SPI EEPROM Clock 2 MHz
Parameter
Microwire EEPROM Clock
Min
Typ
Max
1
Unit
MHz
Table 17. AC Test Loads for General Output Pins
Symbol
CL CL CL CL TDO SDP[3:0] EEDI, EESK LED[3:0]
Signal Name
Value
10 16 18 20
Units
pF pF pF pF
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82541ER Gigabit Ethernet Controller
CL
Figure 2. AC Test Loads for General Output Pins
4.5 4.5.1
4.5.1.1
Timing Specifications PCI Bus Interface
PCI Bus Interface Clock
Table 18. PCI Bus Interface Clock Parameters
PCI 66 MHz Symbol
TCYC TH TL
PCI 33 MHz Units Min
30 11 11
Parametera Min
CLK cycle time CLK high time CLK low time CLK slew rate RST# slew rateb 15 6 6 1.5 50 4
Max
30
Max
ns ns ns 4 V/ns mV/ns
1 50
a. Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate must be met across the minimum peak-to-peak portion of the clock waveform as shown. b. The minimum RST# slew rate applies only to the rising (de-assertion) edge of the reset signal and ensures that system noise cannot render a monotonic signal to appear bouncing in the switching range.
Tcyc
3.3 V Clock
Th 0.6 Vcc
0.4 Vcc p-to-p (minimum)
0.5 Vcc 0.4 Vcc 0.3 Vcc
0.2 Vcc Tl
PCI Clock Timing.vsd
Figure 3. PCI Clock Timing
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82541ER Gigabit Ethernet Controller
4.5.1.2
PCI/PCI-X Bus Interface Timing
Table 19. PCI Bus Interface Timing Parameters
PCI 66MHz Symbol Parameter Min
TVAL TVAL(ptp) TON TOFF TSU TSU(ptp) TH CLK to signal valid delay: bussed signals CLK to signal valid delay: pointto-point signals Float to active delay Active to float delay Input setup time to CLK: bussed signals Input setup time to CLK: point-topoint signals Input hold time from CLK 3 5 0 2 2 2 14 7 10, 12 0
PCI 33 MHz Units Min
2 2 2 28
Max
6 6
Max
11 12 ns ns ns ns ns ns ns
NOTES: 1. Output timing measurements are as shown. 2. REQ# and GNT# signals are point-to-point and have different output valid delay and input setup times than bussed signals. GNT# has a setup of 10 ns; REQ# has a setup of 12 ns. All other signals are bussed. 3. Input timing measurements are as shown.
VTH PCI_CLK VTEST VTL
Output Delay
output current leakage current
VTEST VSTEP (3.3V Signalling)
Tri-State Output TON TOFF
Figure 4. PCI Bus Interface Output Timing Measurement
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82541ER Gigabit Ethernet Controller
VTH PCI_CLK VTEST VTL TSU VTH Input VTL VTEST Input Valid VTEST VMAX TH
Figure 5. PCI Bus Interface Input Timing Measurement Conditions
Table 20. PCI Bus Interface Timing Measurement Conditions
Symbol
VTH VTL VTEST
Parameter
Input measurement test voltage (high) Input measurement test voltage (low) Output measurement test voltage Input signal slew rate
PCI 66 MHz 3.3 v
0.6 * VCC 0.2 * VCC 0.4 * VCC 1.5
Unit
V V V V/ns
Pin
1/2 inch max.
Test Point
25
10 pF
Figure 6. TVAL (max) Rising Edge Test Load
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82541ER Gigabit Ethernet Controller
Pin
1/2 inch max.
Test Point
25
10 pF
VCC
Figure 7. TVAL (max) Falling Edge Test Load
Figure 8. TVAL (min) Test Load
Pin
1/2 inch max.
Test Point
50 pF
Figure 9. TVAL Test Load (PCI 5 V Signaling Environment)
NOTE: Note: 50 pF load used for maximum times. Minimum times are specified with 0 pF load.
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82541ER Gigabit Ethernet Controller
4.5.2
Link Interface Timing
Table 21. Rise and Fall Times
Symbol
TR TF TR TF
Parameter
Clock rise time Clock fall time Data rise time Data fall time
Condition
0.8 V to 2.0 V 2.0 V to 0.8 V 0.8 to 2.0 V 2.0 V to 0.8 V
Min
0.7 0.7 0.7 0.7
Max
Unit
ns ns ns ns
2.0 V
0.8 V
TR
TF
Figure 10. Link Interface Rise/Fall Timing
4.5.3
EEPROM Interface
Table 22. Link Interface Clock Requirements
Symbol Parametera
Microwire EESK pulse width TPW SPI EESK pulse width
a. The EEPROM clock is derived from a 125 MHz internal clock. TPERIOD x
Min
Typ
TPERIOD x 64 32
Max
Unit
ns ns
Table 23. Link Interface Clock Requirements
Symbol
TDOS TDOH
Parametera
EEDO setup time EEDO hold time
Min
TCYC*2 0
Typ
Max
Unit
ns ns
a. The EE_DO setup and hold time is a function of the PCI bus clock cycle time but is referenced to O_EE_SK.
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82541ER Gigabit Ethernet Controller
5.0
Package and Pinout Information
This section describes the device physical characteristics. The pin number-to-signal mapping is indicated beginning with Table 25.
5.1
Package Information
The 82541ER device is a 196-lead plastic ball grid array (BGA) measuring 15 mm by 15mm. The package dimensions are detailed below. The nominal ball pitch is 1 mm.
1.56 +/-0.19 0.85
30
o
0.40 +/-0.10 0.32 +/-0.04
Seating Plate
Figure 11. 82541ER Mechanical Specifications Note: No changes to existing soldering processes are needed for the 0.32 mm substrate change.
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82541ER Gigabit Ethernet Controller
Detail Area
0.45 Solder Resist Opening
0.60 Metal Diameter
Figure 12. 196 PBGA Package Pad Detail As illustrated in Figure 12, the Ethernet controller package uses solder mask defined pads. The copper area is 0.60 mm and the opening in the solder mask is 0.45mm. The nominal ball sphere diameter is 0.50 mm.
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82541ER Gigabit Ethernet Controller
5.2
Thermal Specifications
The 82541ER device is specified for operation when the ambient temperature (TA) is within the range of 0 C to 70 C. TC (case temperature) is calculated using the equation: TC = TA + P (JA - JC) TJ (junction temperature) is calculated using the equation: TJ = TA + P JA P (power consumption) is calculated by using the typical ICC and nominal VCC. The preliminary thermal resistances are shown in Table 24.
Table 24. Thermal Characteristics
Symbol Parameter Preliminary Value at specified airflow (m/s) 0
JA JC Thermal resistance, junction-to-ambient Thermal resistance, junction-to-case 29 11.1
Units
1
25.0 11.1
2
23.5 11.1 C/Watt C/Watt
Thermal resistances are determined empirically with test devices mounted on standard thermal test boards. Real system designs may have different characteristics due to board thickness, arrangement of ground planes, and proximity of other components. The case temperature measurements should be used to assure that the 82541ER device is operating under recommended conditions.
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82541ER Gigabit Ethernet Controller
5.3
Pinout Information
Table 25. PCI Address, Data and Control Signals
Signal
AD[0] AD[1] AD[2] AD[3] AD[4] AD[5] AD[6] AD[7] AD[8] AD[9] AD[10] AD[11] AD[12] AD[13] AD[14] AD[15]
Pin
N7 M7 P6 P5 N5 M5 P4 N4 P3 N3 N2 M1 M2 M3 L1 L2
Signal
AD[16] AD[17] AD[18] AD[19] AD[20] AD[21] AD[22] AD[23] AD[24] AD[25] AD[26] AD[27] AD[28] AD[29] AD[30] AD[31]
Pin
K1 E3 D1 D2 D3 C1 B1 B2 B4 A5 B5 B6 C6 C7 A8 B8
Signal
C/BE#[0] C/BE#[1] C/BE#[2] C/BE#[3] PAR FRAME# IRDY# TRDY# STOP# DEVSEL# IDSEL VIO
Pin
M4 L3 F3 C4 J1 F2 F1 G3 H1 H3 A4 G2
Table 26. PCI Arbitration Signals
Signal
REQ# GNT#
Pin
C3 J3
Table 27. Interrupt Signals
Signal
INTA#
Pin
H2
Table 28. System Signals
Signal
CLK M66EN
Pin
G1 C2 RST#
Signal
Pin
B9
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82541ER Gigabit Ethernet Controller
Table 29. Error Reporting Signals
Signal
SERR#
Pin
A2
Signal
PERR#
Pin
J2
Table 30. Power Management Signals
Signal
LAN_PWR_GOOD AUX_PWR
Pin
A9 J12
Table 31. Serial EEPROM Interface Signals
Signal
EESK EEDO
Pin
M10 N10 EEDI
Signal
Pin
P10 J4
Signal
EECS
Pin
P7
EEMODE
Table 32. Serial FLASH Interface Signals
Signal
FLSH_SCK FLSH_SO/LAN_DISABLE#
Pin
N9 P9
Signal
FLSH_SI
Pin
M11
Signal
FLSH_CE#
Pin
M9
Table 33. LED Signals
Signal
LINK_UP# ACTIVITY#
Pin
A12 C11
Signal
LINK100# LINK1000#
Pin
B11 B12
Table 34. Other Signals
Signal
SDP[0] SDP[1] N14 P13
Pin
Signal
SDP[2] SDP[3] N13
Pin
M12
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82541ER Gigabit Ethernet Controller
Table 35. IEEE Test Signals
Signal
IEEE_TEST-
Pin
D14
Signal
IEEE_TEST+
Pin
B14
Table 36. PHY Signals
Signal
MDI[0]MDI[0]+ MDI[1]MDI[1]+ C14 C13 E14 E13
Pin
Signal
MDI[2]MDI[2]+ MDI[3]MDI[3]+ F14 F13 H14 H13
Pin
Signal
XTAL1 XTAL2 K14 J14
Pin
Table 37. Test Interface Signals
Signal
JTAG_TCK JTAG_TDI
Pin
L14 M13
Signal
JTAG_TDO JTAG_TMS
Pin
M14 L12
Signal
JTAG_TRST# TEST
Pin
L13 A13
Table 38. Digital Power Signals
Signal
3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V A3 A7 A11 E1 K3 K4 K13 N6 N8 P2 P12
Pin
1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V
Signal
G5 G6 H5 H6 H7 H8 J10 J11 J5 J6 J7 J8
Pin
1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V
Signal
J9 K10 K11 K5 K6 K7 K8 K9 L10 L4 L5 L9
Pin
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82541ER Gigabit Ethernet Controller
Table 39. Analog Power Signals
Signal
ANALOG_1.2V ANALOG_1.2V ANALOG_1.2V ANALOG_1.2V E11 E12 G13 H11
Pin
Signal
ANALOG_1.8V ANALOG_1.8V PLL_1.2V PLL_1.2V D11
Pin
Signal
CLKR_1.8V XTAL_1.8V D12 J13
Pin
G12 G4 H4
Table 40. Grounds and No Connect Signals
Signal
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
Pin
B3 B7 C10 D5 D6 D7 D8 E10 E2 E5 E6 E7 E8 E9 F4 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
Signal
Pin
F5 F6 F7 F8 F9 F10 G7 G8 G9 G10 H9 H10 K2 L6 L11
Signal
VSS VSS VSS VSS AVSS AVSS AVSS AVSS AVSS AVSS NC NC NC NC NC
Pin
M6 N1 N12 P8 C12 D13 F11 G11 G14 K12 A1 A14 D9 D10 H12
Signal
NC NC NC Pull up to VCCa Pull up to VCCa Pull up to VCCa VSS VSS NC NC NC NC NC NC NC
Pin
L8 P1 P14 A10 B10 C9 D4 E4 A6 C5 F12 L7 M8 N11 C8
a. Use a 1 K resistor.
Table 41. Voltage Regulation Control Signals
Signal
CTRL18
Pin
B13
Signal
CTRL12
Pin
P11
Datasheet
35
82541ER Gigabit Ethernet Controller
Table 42. Signal Names in Pin Order (Sheet 1 of 6)
Signal Name
NC SERR# 3.3V IDSEL AD[25] NC 3.3V AD[30] LAN_PWR_GOOD Pull up to VCCa 3.3V LINK_LED# TEST NC AD[22] AD[23] VSS AD[24] AD[26] AD[27] VSS AD[31] RST# Pull up to VCCa LINK100# LINK1000# CTRL18 IEEE_TEST+ AD[21] M66EN REQ# C/BE#[3] NC
Pin
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 C1 C2 C3 C4 C5
36
Datasheet
82541ER Gigabit Ethernet Controller
Table 42. Signal Names in Pin Order (Sheet 2 of 6) (Continued)
AD[28] AD[29] NC Pull up to VCCa VSS ACTIVITY# AVSS MDI[0]+ MDI[0]AD[18] AD[19] AD[20] VSS VSS VSS VSS VSS NC NC ANALOG_1.8V CLKR_1.8V AVSS IEEE_TEST3.3V VSS AD[17] VSS VSS VSS VSS VSS VSS VSS ANALOG_1.2V ANALOG_1.2V MDI[1]+ C6 C7 C8 C9 C10 C11 C12 C13 C14 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13
Datasheet
37
82541ER Gigabit Ethernet Controller
Table 42. Signal Names in Pin Order (Sheet 3 of 6) (Continued)
MDI[1]IRDY# FRAME# C/BE#[2] VSS VSS VSS VSS VSS VSS VSS AVSS NC MDI[2]+ MDI[2]CLK VIO TRDY# PLL_1.2V 1.2V 1.2V VSS VSS VSS VSS AVSS ANALOG_1.8V ANALOG_1.2V AVSS STOP# INTA# DEVSEL# PLL_1.2V 1.2V 1.2V 1.2V E14 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 H1 H2 H3 H4 H5 H6 H7
38
Datasheet
82541ER Gigabit Ethernet Controller
Table 42. Signal Names in Pin Order (Sheet 4 of 6) (Continued)
1.2V VSS VSS ANALOG_1.2V NC MDI[3]+ MDI[3]PAR PERR# GNT# EEMODE 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V AUX_PWR XTAL_1.8V XTAL2 AD[16] VSS 3.3V 3.3V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V AVSS 3.3V XTAL1 AD[14] H8 H9 H10 H11 H12 H13 H14 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 L1
Datasheet
39
82541ER Gigabit Ethernet Controller
Table 42. Signal Names in Pin Order (Sheet 5 of 6) (Continued)
AD[15] C/BE#[1] 1.2V 1.2V VSS NC NC 1.2V 1.2V VSS JTAG_TMS JTAG_TRST# JTAG_TCK AD[11] AD[12] AD[13] C/BE#[0]# AD[5] VSS AD[1] NC FLSH_CE# EESK FLSH_SI SDP[3] JTAG_TDI JTAG_TDO VSS AD[10] AD[9] AD[7] AD[4] 3.3V AD[0] 3.3V FLSH_SCK L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 N1 N2 N3 N4 N5 N6 N7 N8 N9
40
Datasheet
82541ER Gigabit Ethernet Controller
Table 42. Signal Names in Pin Order (Sheet 6 of 6) (Continued)
EEDO NC VSS SDP[2] SDP[0] NC 3.3V AD[8] AD[6] AD[3] AD[2] EECS VSS FLSH_SO EEDI CTRL12 3.3V SDP[1] NC
a. Use a 1 K resistor.
N10 N11 N12 N13 N14 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14
Datasheet
41
82541ER Gigabit Ethernet Controller
5.4
A 1
NC
Visual Pin Assignments
B
AD[22]
C
AD[21]
D
AD[18]
E
3.3V
F
IRDY#
G
CLK
H
STOP#
J
PAR
K
AD[16]
L
AD[14]
M
AD[11]
N
VSS
P
NC
2
SERR#
AD[23]
M66EN
AD[19]
VSS
FRAME#
VIO
INTA#
PERR#
VSS
AD[15]
AD[12]
AD[10]
3.3V
3
3.3V
VSS
REQ#
AD[20]
AD[17]
C/BE#[2]
TRDY#
DVSEL#
GNT#
3.3V
C/B3#[1]
AD[13]
AD[9]
AD[8]
4
IDSEL
AD[24]
C/BE#[3]
VSS
VSS
VSS
PLL_1.2V
PLL_1.2V
EEMODE
3.3V
1.2V
C/BE#[0]
AD[7]
AD[6]
5
AD[25]
AD[26]
NC
VSS
VSS
VSS
1.2V
1.2V
1.2V
1.2V
1.2V
AD[5]
AD[4]
AD[3]
6
NC
AD[27]
AD[28]
VSS
VSS
VSS
1.2V
1.2V
1.2V
1.2V
VSS
VSS
3.3V
AD[2]
7
3.3V
VSS
AD[29]
VSS
VSS
VSS
VSS
1.2V
1.2V
1.2V
NC
AD[1]
AD[0]
EECS
8
AD[30]
AD[31]
NC
VSS
VSS
VSS
VSS
1.2V
1.2V
1.2V
NC
NC
3.3V
VSS
9
LAN_PWR_ GOOD
RST#
Pull Up To VCC
NC
VSS
VSS
VSS
VSS
1.2V
1.2V
1.2V
FLSH_CE#
FLSH_SCK
FLSH_SO
10
Pull Up To VCC
Pull Up To VCC
VSS
NC
VSS
VSS
VSS
VSS
1.2V
1.2V
1.2V
EESK
EEDO
EEDI
11
3.3V
LINK100#
ACTIVITY#
ANALOG_ 1.8V
ANALOG_ 1.2V
AVSS
AVSS
ANALOG_ 1.2V
1.2V
1.2V
VSS
FLSH_SI
NC
CTRL12
12
LINK_LED#
LINK1000#
AVSS
CLKR_ 1.8V
ANALOG_ 1.2V
NC
ANALOG_ 1.8V
NC
AUX_PWR
AVSS
JTAG_TMS
SDP[3]
VSS
3.3V
13
TEST
CTRL18
MDI[0]+
AVSS
MDI[1]+
MDI[2]+
ANALOG_ 1.2V
MDI[3]+
XTAL_1.8V
3.3V
JTAG_TRST#
JTAG_TDI
SDP[2]
SDP[1]
14
NC
IEEE_TEST+
MDI[0]-
IEEE_TEST-
MDI[1]-
MDI[2]-
AVSS
MDI[3]-
XTAL2
XTAL1
JTAG_TCK
JTAG_TDO
SDP[0]
NC
Pins A10, B-10, and C9 - Use 1K ohm resistors.
Figure 13. Visual Pin Assignments
42
Datasheet

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